
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
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(2/2)
Clearing is disabled
Clearing is enabled (after the clearing, restarts counting)
ECLRn
0
1
TMn register clear enable/disable specification by external clear input (TCLRn)
The register operates as a capture register.
The register operates as a compare register.
CMSn1
0
1
Capture/compare register (CCn1) operation mode selection
The register operates as a capture register.
The register operates as a compare register.
CMSn0
0
1
Capture/compare register (CCn0) operation mode selection
Clearing is disabled
Clearing is enabled (if CCn0 and TMn match during a compare operation,
TMn is cleared)
CCLRn
0
1
TMn register clear enable/disable specification during compare operation
Low level
High level
ALVn
0
1
External pulse output (TOn) active level specification
The initial value of the ALVn bit is 1.
Specifies the input clock (internal).
Specifies the external clock (TIn0).
ETIn
0
1
Count clock external/internal switch specification
When ETIn bit = 0, the clock can be selected according to the CSn2 to CSn0 bits
of TMCn0.
When ETIn bit = 1, the valid edge can be selected according to the TESn1 and
TESn0 bit specifications of SESn.
Remark
A reset takes precedence for the flip-flop of the TOn output (n = 0, 1).